Lineup
CPU Units
Built-in USB port
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CPU Unit | Specifications | Model | ||||
---|---|---|---|---|---|---|
CPU type | Power supply |
Output method | Inputs | Outputs | ||
CP1L-M CPU Units with 60 Points |
Memory capacity: 10K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 36 | 24 | CP1L-M60DR-A |
Transistor output (sinking) |
CP1L-M60DT-A | |||||
DC power supply |
Relay output | CP1L-M60DR-D | ||||
Transistor output (sinking) |
CP1L-M60DT-D | |||||
Transistor output (sourcing) |
CP1L-M60DT1-D | |||||
CP1L-M CPU Units with 40 Points |
Memory capacity: 10K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 24 | 16 | CP1L-M40DR-A |
Transistor output (sinking) |
CP1L-M40DT-A | |||||
DC power supply |
Relay output | CP1L-M40DR-D | ||||
Transistor output (sinking) |
CP1L-M40DT-D | |||||
Transistor output (sourcing) |
CP1L-M40DT1-D | |||||
CP1L-M CPU Units with 30 Points |
Memory capacity: 10K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 18 | 12 | CP1L-M30DR-A |
Transistor output (sinking) |
CP1L-M30DT-A | |||||
DC power supply |
Relay output | CP1L-M30DR-D | ||||
Transistor output (sinking) |
CP1L-M30DT-D | |||||
Transistor output (sourcing) |
CP1L-M30DT1-D | |||||
CP1L-L CPU Units with 20 Points |
Memory capacity: 5K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 12 | 8 | CP1L-L20DR-A |
Transistor output (sinking) |
CP1L-L20DT-A | |||||
DC power supply |
Relay output | CP1L-L20DR-D | ||||
Transistor output (sinking) |
CP1L-L20DT-D | |||||
Transistor output (sourcing) |
CP1L-L20DT1-D | |||||
CP1L-L CPU Units with 14 Points |
Memory capacity: 5K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 8 | 6 | CP1L-L14DR-A |
Transistor output (sinking) |
CP1L-L14DT-A | |||||
DC power supply |
Relay output | CP1L-L14DR-D | ||||
Transistor output (sinking) |
CP1L-L14DT-D | |||||
Transistor output (sourcing) |
CP1L-L14DT1-D | |||||
CP1L-L CPU Units with 10 Point |
Memory capacity: 5K steps High-speed counters: 100 kHz, 4 axes Pulse outputs: 100 kHz, 2 axes (Models with transistor outputs only) |
AC power supply |
Relay output | 6 | 4 | CP1L-L10DR-A |
Transistor output (sinking) |
CP1L-L10DT-A | |||||
DC power supply |
Relay output | CP1L-L10DR-D | ||||
Transistor output (sinking) |
CP1L-L10DT-D | |||||
Transistor output (sourcing) |
CP1L-L10DT1-D |
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Note:
1. Refer to “Models and Software Versions” about supported software.
2. Refer to “Option Unit Specifications” about supported Option Units.
Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
EtherNet/IPTM is the trademarks of ODVA.
Other company names and product names in this document are the trademarks or registered trademarks of their respective companies.
Specifications
General Specifications
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Type | AC power supply models | DC power supply models |
---|---|---|
Model | CP1L-[][][]-A | CP1L-[][][]-D |
Power supply | 100 to 240 VAC 50/60 Hz | 24 VDC |
Operating voltage range |
85 to 264 VAC | 20.4 to 26.4 VDC |
Power consumption | 50 VA max. (CP1L-M60/-M40/-M30[][]-A) 30 VA max. (CP1L-L20/-L14/-L10[][]-A) |
20 W max. (CP1L-EM40/-EM30/-M60/-M40/ -M30[][]-D) 13 W max. (CP1L-EL20/-L20/-L14/ -L10[][]-D) |
Inrush current * | 100 to 120 VAC inputs: 20 A max. (for cold start at room temperature) 8 ms max. 200 to 240 VAC inputs: 40 A max. (for cold start at room temperature), 8 ms max. |
30 A max. (for cold start at room temperature) 20 ms max. |
External power supply | 300 mA at 24 VDC (CP1L-M60/-M40/ -M30[][]-A) 200 mA at 24 VDC (CP1L-L20/-L14/ -L10[][]-A) |
None |
Insulation resistance | 20 MΩ min. (at 500 VDC) between the external AC terminals and GR terminals |
No insulation between primary and secondary for DC power supply |
Dielectric strength | 2,300 VAC at 50/60 Hz for 1 min between the external AC and GR terminals, leakage current: 5 mA max. |
No insulation between primary and secondary for DC power supply |
Noise immunity | Conforms to IEC 61000-4-4. 2 kV (power supply line) | |
Vibration resistance | CP1L-L/M: Conforms to JIS C60068-2-6. 10 to 57 Hz, 0.075-mm amplitude, 57 to 150 Hz, acceleration: 9.8 m/s2 in X, Y, and Z directions for 80 minutes each. Sweep time: 8 minutes × 10 sweeps = total time of 80 minutes) CP1L-EL/EM: 5 to 8.4 Hz, 3.5 mm amplitude, 8.4 to 150 Hz, acceleration: 9.8 m/s2 in X, Y, and Z directions for 100 minutes each (time coefficient of 10 minutes × coefficient factor of 10 = total time of 100 minutes) |
|
Shock resistance | Conforms to JIS C60068-2-27. 147 m/s2 three times each in X, Y, and Z directions | |
Ambient operating temperature |
0 to 55°C | |
Ambient humidity | 10% to 90% (with no condensation) | |
Ambient operating environment |
No corrosive gas | |
Ambient storage temperature |
-20 to 75°C (Excluding battery.) | |
Power holding time | 10 ms min. | 2 ms min. |
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* The above values are for a cold start at room temperature for an AC power supply, and for a cold start for a DC power supply.
• A thermistor (with low-temperature current suppression characteristics) is used in the inrush current control circuitry for the AC power supply. The thermistor will not be sufficiently cooled if the ambient temperature is high or if a hot start is performed when the power supply has been OFF for only a short time. In those cases the inrush current values may be higher (as much as two times higher) than those shown above. Always allow for this when selecting fuses and breakers for external circuits.
• A capacitor charge-type delay circuit is used in the inrush current control circuitry for the DC power supply. The capacitor will not be charged if a hot start is performed when the power supply has been OFF for only a short time, so in those cases the inrush current values may be higher (as much as two times higher) than those shown above.
Performance Specifications
CP1L CPU Unit (EM/EL Type)
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Type | CP1L-EM40 (40 points) | CP1L-EM30 (30 points) | CP1L-EL20 (20 points) | |
---|---|---|---|---|
Models | CP1L-EM40D[]-[] | CP1L-EM30D[]-[] | CP1L-EL20D[]-[] | |
Control method | Stored program method | |||
I/O control method | Cyclic scan with immediate refreshing | |||
Program language | Ladder diagram | |||
Function blocks | Maximum number of function block definitions: 128 Maximum number of instances: 256 Languages usable in function block definitions: Ladder diagrams, structured text (ST) |
|||
Instruction length | 1 to 7 steps per instruction | |||
Instructions | Approx. 500 (function codes: 3 digits) | |||
Instruction execution time | Basic instructions: 0.55 μs min. Special instructions: 4.1 μs min. | |||
Common processing time | 0.4ms | |||
Program capacity | 10K steps | 5K steps | ||
FB program memory |
10K steps | |||
Number of tasks | 288 (32 cyclic tasks and 256 interrupt tasks) | |||
Scheduled interrupt tasks |
1 (interrupt task No. 2, fixed) | |||
Input interrupt tasks |
6 (interrupt task No. 140 to 145, fixed) | |||
(High-speed counter interrupts and interrupt tasks specified by external interrupts can also be executed.) |
||||
Maximum subroutine number |
256 | |||
Maximum jump number | 256 | |||
I/O areas |
Input Area | 1,600 bits (100 words) CIO 0 to CIO 99 | ||
Built-in Input Area |
24 bits: CIO 0.00 to CIO 0.11 and CIO 1.00 to CIO 1.11 |
18 bits: CIO 0.00 to CIO 0.11 and CIO 1.00 to CIO 1.05 |
12 bits: CIO 0.00 to CIO 0.11 | |
Output Area | 1,600 bits (100 words) CIO 100 to CIO 199 | |||
Built-in Output Area |
16 bits: CIO 100.00 to CIO 100.07 and CIO 101.00 to CIO 101.07 |
12 bits: CIO 100.00 to CIO 100.07 and CIO 101.00 to CIO 101.03 |
8 bits: CIO 100.00 to CIO 100.07 |
|
1:1 Link Area | 256 bits (16 words): CIO 3000.00 to CIO 3015.15 (CIO 3000 to CIO 3015) | |||
Serial PLC Link Area |
1,440 bits (90 words): CIO 3100.00 to CIO 3189.15 (CIO 3100 to CIO 3189) | |||
Work bits | 4,800 bits (300 words): CIO 1200.00 to CIO 1499.15 (words CIO 1200 to CIO 1499) 6,400 bits (400 words): CIO 1500.00 to CIO 1899.15 (words CIO 1500 to CIO 1899) 15,360 bits (960 words): CIO 2000.00 to CIO 2959.15 (words CIO 2000 to CIO 2959) 9,600 bits (600 words): CIO 3200.00 to CIO 3799.15 (words CIO 3200 to CIO 3799) 37,504 bits (2,344 words): CIO 3800.00 to CIO 6143.15 (words CIO 3800 to CIO 6143) |
|||
TR Area | 16 bits: TR0 to TR15 | |||
Holding Area | 8,192 bits (512 words): H0.00 to H511.15 (H0 to H511) | |||
AR Area | Read-only (Write-prohibited): 7168 bits (448 words): A0.00 to A447.15 (A0 to A447) Read/Write: 8192 bits (512 words): A448.00 to A959.15 (A448 to A959) |
|||
Timers | 4,096 timer numbers: T0 to T4095 | |||
Counters | 4,096 counter numbers: C0 to C4095 | |||
DM Area | 32 Kwords: D0 to D32767 | 10 Kwords: D0 to D9999, D32000 to D32767 |
||
Data Register Area | 16 registers (16 bits): DR0 to DR15 | |||
Index Register Area | 16 registers (32 bits): IR0 to IR15 | |||
Task Flag Area | 32 flags (32 bits): TK0000 to TK0031 | |||
Trace Memory | 4,000 words (500 samples for the trace data maximum of 31 bits and 6 words.) | |||
Memory Cassette | A special Memory Cassette (CP1W-ME05M) can be mounted. Note: Can be used for program backups and auto-booting. |
|||
Clock function | Supported. Accuracy (monthly deviation): -4.5 min to -0.5 min (ambient temperature: 55°C), -2.0 min to +2.0 min (ambient temperature: 25°C), -2.5 min to +1.5 min (ambient temperature: 0°C) |
|||
Communications functions | Built-in Ethernet Port (Connecting Support Software, Message Communications, Socket Service) |
|||
A maximum of two Serial Communications Option Boards can be mounted. |
A maximum of one Serial Communications Option Board can be mounted. |
|||
Memory backup | Flash memory: User programs, parameters (such as the PLC Setup), comment data, and the entire DM Area can be saved to flash memory as initial values. Battery backup: The Holding Area, DM Area, and counter values (flags, PV) are backed up by a battery. |
|||
Battery service life | Service life expectancy is 5 years at 25°C, less at higher temperatures. (From 0.75 to 5 years depending on model, power supply rate, and ambient temperature.) |
|||
Built-in input terminals | 40 (24 inputs, 16 outputs) | 30 (18 inputs, 12 outputs) | 20 (12 inputs, 8 outputs) | |
Number of connectable Expansion Units and Expansion I/O Units |
CP-series Expansion Unit and Expansion I/O Units: 3 max. |
CP-series Expansion Units and Expansion I/O Units: 1 max. |
||
Max. number of I/O points | 160 (40 built in + 40 per Expansion (I/O) Unit x 3 Units) |
150 (30 built in + 40 per Expansion (I/O) Unit x 3 Units) |
60 (20 built in + 40 per Expansion (I/O) Unit x 1 Unit) |
|
Interrupt inputs | 6 inputs (Response time: 0.3 ms) | |||
Interrupt inputs counter mode |
6 inputs (Response frequency: 5 kHz max. for all interrupt inputs), 16 bits Up or down counters |
|||
Quick-response inputs | 6 points (Min. input pulse width: 50 μs max.) | |||
Scheduled interrupts | 1 | |||
High-speed counters | 4 inputs/2 axes (24 VDC) Differential phases (4x), 50 kHz Single-phase (pulse plus direction, up/down, increment), 100 kHz Value range: 32 bits, Linear mode or ring mode Interrupts: Target value comparison or range comparison |
|||
Pulse outputs (models with transistor outputs only) |
Pulse outputs | Trapezoidal or S-curve acceleration and deceleration (Duty ratio: 50% fixed) 2 outputs, 1 Hz to 100 kHz (CCW/CW or pulse plus direction) |
||
PWM outputs | Duty ratio: 0.0% to 100.0% (specified in increments of 0.1% or 1%) 2 outputs, 0.1 to 6553.5 Hz or 1 to 32,800 Hz (Accuracy: +1%/0% at 0.1 Hz to 10,000 Hz and +5%/0% at 10,000 Hz to 32,800 Hz) |
|||
Analog input | 2 input (Resolution: 1/1000, Input range: 0 to 10 V). Not isolated. |
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CP1L CPU Unit (M/L Type)
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Type | CP1L-M60 (60 points) |
CP1L-M40 (40 points) |
CP1L-M30 (30 points) |
CP1L-L20 (20 points) |
CP1L-L14 (14 points) |
CP1L-L10 (10 points) |
|
---|---|---|---|---|---|---|---|
Models | CP1L- M60[][]-[] |
CP1L- M40[][]-[] |
CP1L- M30[][]-[] |
CP1L- L20[][]-[] |
CP1L- L14[][]-[] |
CP1L- L10[][]-[] |
|
Control method | Stored program method | ||||||
I/O control method | Cyclic scan with immediate refreshing | ||||||
Program language | Ladder diagram | ||||||
Function blocks | Maximum number of function block definitions: 128 Maximum number of instances: 256 Languages usable in function block definitions: Ladder diagrams, structured text (ST) |
||||||
Instruction length | 1 to 7 steps per instruction | ||||||
Instructions | Approx. 500 (function codes: 3 digits) | ||||||
Instruction execution time |
Basic instructions: 0.55 μs min. Special instructions: 4.1 μs min. | ||||||
Common processing time |
0.4 ms | ||||||
Program capacity | 10K steps | 5K steps | |||||
Number of tasks | 288 (32 cyclic tasks and 256 interrupt tasks) | ||||||
Scheduled interrupt tasks |
1 (interrupt task No. 2, fixed) | ||||||
Input interrupt tasks |
6 (interrupt task No. 140 to 145, fixed) | 4 (interrupt task No. 140 to 143, fixed) |
2 (interrupt task No. 140 to 141, fixed) |
||||
(Interrupt tasks can also be specified and executed for high-speed counter interrupts and executed.) |
|||||||
Maximum subroutine number |
256 | ||||||
Maximum jump number | 256 | ||||||
I/O areas |
Input Area | 1,600 bits (100 words) CIO 0 to CIO 99 | |||||
Built-in Input Area |
36 bits: CIO 0.00 to CIO 0.11 and CIO 1.00 to CIO 1.11 and CIO 2.00 to CIO 2.11 |
24 bits: CIO 0.00 to CIO 0.11 and CIO 1.00 to CIO 1.11 |
18 bits: CIO 0.00 to CIO 0.11 and CIO 1.00 to CIO 1.05 |
12 bits: CIO 0.00 to CIO 0.11 |
8 bits: CIO 0.00 to CIO 0.07 |
6 bits: CIO 0.00 to CIO 0.05 |
|
Output Area | 1,600 bits (100 words) CIO 100 to CIO 199 | ||||||
Built-in Output Area |
24 bits: CIO 100.00 to CIO 100.07 and CIO 101.00 to CIO 101.07 and CIO 102.00 to CIO 102.07 |
16 bits: CIO 100.00 to CIO 100.07 and CIO 101.00 to CIO 101.07 |
12 bits: CIO 100.00 to CIO 100.07 and CIO 101.00 to CIO 100.03 |
8 bits: CIO 100.00 to CIO 100.07 |
6 bits: CIO 100.00 to CIO 100.05 |
4 bits: CIO 100.00 to CIO 100.03 |
|
1:1 Link Area |
1,024 bits (64 words): CIO 3000.00 to CIO 3063.15 (CIO 3000 to CIO 3063) | ||||||
Serial PLC Link Area |
1,440 bits (90 words): CIO 3100.00 to CIO 3189.15 (CIO 3100 to CIO 3189) | ||||||
Work bits | 8,192 bits (512 words): W000.00 to W511.15 (W0 to W511) CIO Area: 37,504 bits (2,344 words): CIO 3800.00 to CIO 6143.15 (CIO 3800 to CIO 6143) |
||||||
TR Area | 16 bits: TR0 to TR15 | ||||||
Holding Area | 8,192 bits (512 words): H0.00 to H511.15 (H0 to H511) | ||||||
AR Area | Read-only (Write-prohibited): 7168 bits (448 words): A0.00 to A447.15 (A0 to A447) Read/Write: 8192 bits (512 words): A448.00 to A959.15 (A448 to A959) |
||||||
Timers | 4,096 timer numbers: T0 to T4095 | ||||||
Counters | 4,096 counter numbers: C0 to C4095 | ||||||
DM Area | 32 Kwords: D0 to D32767 | 10 Kwords: D0 to D9999, D32000 to D32767 |
|||||
Data Register Area | 16 registers (16 bits): DR0 to DR15 | ||||||
Index Register Area | 16 registers (32 bits): IR0 to IR15 | ||||||
Task Flag Area | 32 flags (32 bits): TK0000 to TK0031 | ||||||
Trace Memory | 4,000 words (500 samples for the trace data maximum of 31 bits and 6 words.) | ||||||
Memory Cassette | A special Memory Cassette (CP1W-ME05M) can be mounted. Note: Can be used for program backups and auto-booting. |
||||||
Clock function | Supported. Accuracy (monthly deviation): -4.5 min to -0.5 min (ambient temperature: 55°C), -2.0 min to +2.0 min (ambient temperature: 25°C), -2.5 min to +1.5 min (ambient temperature: 0°C) |
||||||
Communications functions |
One built-in peripheral port (USB 1.1): For connecting Support Software only. | ||||||
A maximum of two Serial Communications Option Boards can be mounted. |
A maximum of one Serial Communications Option Board can be mounted. |
Not supported. |
|||||
A maximum of two Ethernet Option Board can be mounted. When using CP1W-CIF41 Ver.1.0, one Ethernet Option Board can be mounted. |
A maximum of one Ethernet Option Board can be mounted. |
Not supported. |
|||||
Memory backup | Flash memory: User programs, parameters (such as the PLC Setup), comment data, and the entire DM Area can be saved to flash memory as initial values. Battery backup: The Holding Area, DM Area, and counter values (flags, PV) are backed up by a battery. |
||||||
Battery service life | Service life expectancy is 5 years at 25°C, less at higher temperatures. (From 0.75 to 5 years depending on model, power supply rate, and ambient temperature.) |
||||||
Built-in input terminals |
60 (36 inputs, 24 outputs) |
40 (24 inputs, 16 outputs) |
30 (18 inputs, 12 outputs) |
20 (12 inputs, 8 outputs) |
14 (8 inputs, 6 outputs) |
10 (6 inputs, 4 outputs) |
|
Number of connectable Expansion Units and Expansion I/O Units |
CP-series Expansion Unit and Expansion I/O Units: 3 max. |
CP-series Expansion Units and Expansion I/O Units: 1 max. |
Not supported. |
||||
Max. number of I/O points |
180 (60 built in + 40 per Expansion (I/O) Unit × 3 Units) |
160 (40 built in + 40 per Expansion (I/O) Unit × 3 Units) |
150 (30 built in + 40 per Expansion (I/O) Unit × 3 Units) |
60 (20 built in + 40 per Expansion (I/O) Unit × 1 Unit) |
54 (14 built in + 40 per Expansion (I/O) Unit × 1 Unit) |
10 (10 built in) |
|
Interrupt inputs | 6 inputs (Response time: 0.3 ms) | 4 inputs (Response time: 0.3 ms) |
2 inputs (Response time: 0.3 ms) |
||||
Interrupt inputs counter mode |
6 inputs (Response frequency: 5 kHz max. for all interrupt inputs), 16 bits Up or down counters |
4 inputs (Response frequency: 5 kHz max. for all interrupt inputs), 16 bits Up or down counters |
2 inputs (Response frequency: 5 kHz max. for all interrupt inputs), 16 bits Up or down counters |
||||
Quick-response inputs | 6 points (Min. input pulse width: 50 μs max.) | 4 points (Min. input pulse width: 50 μs max.) |
2 points (Min. input pulse width: 50 μs max.) |
||||
Scheduled interrupts | 1 | ||||||
High-speed counters | 4 inputs/2 axes (24 VDC): Differential phases (4x), 50 kHz Single-phase (pulse plus direction, up/down, increment), 100 kHz Value range: 32 bits, Linear mode or ring mode Interrupts: Target value comparison or range comparison |
||||||
Pulse outputs (models with transistor outputs only) |
Pulse outputs |
Trapezoidal or S-curve acceleration and deceleration (Duty ratio: 50% fixed) 2 outputs, 1 Hz to 100 kHz (CCW/CW or pulse plus direction) |
|||||
PWM outputs |
Duty ratio: 0.0% to 100.0% (specified in increments of 0.1% or 1%) 2 outputs, 0.1 to 6553.5 Hz or 1 to 32,800 Hz (Accuracy: +1%/0% at 0.1 Hz to 10,000 Hz and +5%/0% at 10,000 Hz to 32,800 Hz) |
||||||
Analog control | 1 (Setting range: 0 to 255) | ||||||
Analog input | 1 input (Resolution: 1/256, Input range: 0 to 10 V). Not isolated. |
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